Implementing a circuit design within an integrated circuit (IC), whether a programmable IC or an application specific IC (ASIC), entails processing the circuit design through a design flow. The design flow includes multiple, different stages. These stages generally include synthesis, placement, and routing.
Synthesis refers to the process of converting, or translating, an abstract, programmatic description of a circuit into a low-level design implementation. The abstract, programmatic description of the circuit describes behavior of the circuit and is also referred to as a “behavioral description” or a “register transfer level (RTL) description” of the circuit. The behavioral description is often specified using a hardware description language (HDL). The low-level design implementation generated through synthesis typically is specified as inter-connected logic gates.
Synthesis may also include mapping. Mapping is the process of correlating, or matching, the logic gates of the low-level circuit design to the various types of circuit blocks or resources that are actually available in the particular IC in which the circuit design is to be implemented, i.e., the “target IC.” For example, since a lookup table (LUT) may implement a complex function, one or more logic gates of the low-level design implementation may be mapped to a single LUT, or other programmable tile of the target IC. The mapped circuit design specifies the same functionality as the low-level design implementation, albeit in terms of the particular circuit blocks available on the target IC as opposed to low-level logic gates.
Placement is the process of assigning elements of the synthesized circuit design to particular instances of circuit blocks and/or resources having specific locations on the target IC. Once placed, a circuit element of the circuit design has a specific location on the target IC as opposed to only being assigned to a particular type of circuit block and/or resource as is the case after mapping and prior to placement. The location of a circuit element of a circuit design, once placed, is the location on the target IC of the instance of the circuit block and/or resource to which the circuit element is assigned. Routing is the process of selecting particular routing resources such as wires, PIPs, PIP settings, and/or other interconnect circuitry to electrically couple the various circuit blocks of the target IC after placement.
Modern circuit designs often have aggressive timing requirements. Significant time is spent processing the circuit design through the design flow in an attempt to meet these timing requirements. LUTs are frequently used to implement significant portions of a user design. As such, timing critical paths often traverse through one or more LUTs. Available electronic design automation (EDA) tools attempt to improve timing of circuit designs through optimization of LUT structures during synthesis. Because detailed timing information for the circuit design is not available during early stages of the design flow, optimization performed during synthesis relies upon generic timing estimates or crude timing approximations.
As such, these early stage optimization efforts may be less effective than expected. In some cases, the early stage optimization efforts are entirely ineffective. For example, in some cases the portions of the circuit design optimized during synthesis are not the critical portions of the circuit design observed in later stages of the design flow. In other cases, incorrect optimization choices made early in the design flow may result in non-convergence of the circuit design.